The present invention relates generally to fabrication of interconnect structures within integrated circuits, and more particularly, to a mechanism for maximizing the nuclei density and uniformity of a palladium surface activation layer formed on a barrier material for minimizing electromigration failure of the interconnect structure.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
Referring to FIG. 1, a cross sectional view is shown of a copper interconnect 102 within a trench 104 formed in an insulating layer 106. The copper interconnect 102 within the insulating layer 106 is formed on a bottom dielectric material 109 deposited on a semiconductor wafer 108 such as a silicon substrate as part of an integrated circuit. The bottom dielectric material 109 may be a hardmask layer, an etch stop layer, or a capping layer comprised of SiO2 (silicon dioxide) or SiN (silicon nitride) for example. Because copper is not a volatile metal, copper cannot be easily etched away in a deposition and etching process as typically used for aluminum metallization. Thus, the copper interconnect 102 is typically formed by etching the trench 104 as an opening within the insulating layer 106, and the trench 104 is then filled with copper typically by an electroplating process, as known to one of ordinary skill in the art of integrated circuit fabrication.
Unfortunately, copper is a mid-bandgap impurity in silicon and silicon dioxide. Thus, copper may diffuse easily into these common integrated circuit materials. Referring to FIG. 1, the insulating layer 106 may be comprised of silicon dioxide or a low dielectric constant insulating material such as organic doped silica, as known to one of ordinary skill in the art of integrated circuit fabrication. The low dielectric constant insulating material has a dielectric constant that is lower than that of pure silicon dioxide (SiO2) for lower capacitance of the interconnect, as known to one of ordinary skill in the art of integrated circuit fabrication.
Copper may easily diffuse into such an insulating layer 106, and this diffusion of copper may degrade the performance of the integrated circuit. Thus, a diffusion barrier material 110 is deposited to surround the copper interconnect 102 within the insulating layer 106 on the sidewalls and the bottom wall of the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The diffusion barrier material 110 is disposed between the copper interconnect 102 and the insulating layer 106 for preventing diffusion of copper from the copper interconnect 102 to the insulating layer 106 to preserve the integrity of the insulating layer 106.
Further referring to FIG. 1, an encapsulating layer 112 is deposited as a passivation layer to encapsulate the copper interconnect 102, as known to one of ordinary skill in the art of integrated circuit fabrication. The encapsulating layer 112 is typically comprised of a dielectric such as silicon nitride, and copper from the copper interconnect 102 does not easily diffuse into such a dielectric of the encapsulating layer 112.
In addition, for forming the copper interconnect, an activation layer 111 is deposited onto the diffusion barrier material 110, and a copper seed layer 103 is deposited onto the activation layer 111. The copper conductive fill 102 is electroplated from the copper seed layer 103 in a copper electroplating deposition process. Processes for forming the diffusion barrier material 110, the activation layer 111, the copper seed layer 103, and the copper conductive fill 102 are known to one of ordinary skill in the art of integrated circuit fabrication.
As the width of the copper interconnect is scaled down to tens of nanometers, a conformal deposition process is used for depositing the diffusion barrier material 110 on the sidewalls and the bottom wall of the interconnect opening. However, the copper seed layer 103 may not readily form on the conformal diffusion barrier material 110 in the typical electroless deposition process for forming the copper seed layer 103. Thus, the activation layer 111 is first deposited on the diffusion barrier material 110, and the activation layer 111 is comprised of a material such as palladium or a tin palladium colloid that promotes deposition of the copper seed layer 103 thereon during the electroless deposition process for the copper seed layer 103. For example, U.S. Pat. No. 6,197,688 to Simpson describes a process for forming the activation layer 111 comprised of a tin and palladium colloid, and U.S. Pat. No. 6,291,082 to Lopatin describes a process for forming the activation layer 111 comprised of palladium.
As the line width of the interconnect structure is continually decreased, the thickness of the diffusion barrier material 110 and the thickness of the activation layer 111 are desired to be minimized to in turn minimize the volume of the diffusion barrier material 110 and the volume of the activation layer 111 within the interconnect opening. Minimizing the volume of the diffusion barrier material 110 and the activation layer 111 in turn maximizes the volume of the copper conductive fill material 102. Generally, diffusion barrier materials and materials of the activation layer 111 have higher resistance than the copper conductive fill material, as known to one of ordinary skill in the art of integrated circuit fabrication. Thus, maximizing the volume of the copper conductive fill material 102 and minimizing the volume of the diffusion barrier material 110 and the activation layer 111 advantageously results in minimizing the resistance of the interconnect structure.
For minimizing the thickness of the diffusion barrier material 110, a conformal deposition process such as a CVD (chemical vapor deposition) process is used for deposition of the diffusion barrier material 110. Referring to FIG. 2, the activation layer 111 that is relatively thin, such as in a range of tens of angstroms for example, is deposited using an activation solution comprised of palladium ions that are reduced, as known to one of ordinary skill in the art of integrated circuit fabrication. The activation layer 111 for example may be comprised of palladium in that case. However, with such a relatively thin activation layer 111, the palladium ions within the activation solution may cause the deposited palladium of the activation layer 111 to agglomerate into clusters 112 within the interconnect opening 104.
Referring to FIGS. 2 and 3, when the copper seed layer 103 is formed from such uneven deposition of the agglomerated palladium activation layer 112, the step coverage of the copper seed layer 103 is also uneven within the interconnect opening 104. In that case, the palladium activation layer 111 and the copper seed layer 103 do not cover some portions of the sidewalls and the bottom wall of the interconnect opening. Referring to FIGS. 3 and 4, when the copper conductive fill 102 is electroplated from the uneven copper seed layer 103, voids 122 may be formed from portions of the sidewalls and the bottom wall of the interconnect opening that are not covered with the copper seed layer 103.
Such voids 122 are particularly disadvantageous for causing electromigration failure within interconnects having scaled down dimensions of tens of nanometers. Nevertheless, the thickness of the activation layer 111 is desired to be scaled down for minimizing resistance of the copper interconnect. However, the prior art, including U.S. Pat. No. 6,197,688 to Simpson and U.S. Pat. No. 6,291,082 to Lopatin do not address prevention of agglomeration of the activation layer 111 as the thickness of the activation layer 111 is further scaled down. Thus, a mechanism is desired for preventing agglomeration of the activation layer 111 as the thickness of the activation layer 111 is further scaled down to eliminate voids for minimizing electromigration failure of the copper interconnect.
Accordingly, in a general aspect of the present invention, the concentration of the Sn (tin) ions in relation to the concentration of the Pd (palladium) ions is increased in the activation bath for preventing agglomeration of the palladium activation layer formed on the diffusion barrier material within an interconnect opening.
In a general aspect of the present invention, in a system and method for fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material.
In another embodiment of the present invention, a layer of silicon rich material is formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material. In that case, a ratio of the tin ion concentration to the palladium ion concentration in the activation bath is adjusted to decrease with an amount of silicon atoms of the layer of silicon rich material deposited on the layer of diffusion barrier material. For example, when the layer of silicon rich material is not deposited on the layer of diffusion barrier material, the ratio of the tin ion concentration to the palladium ion concentration in the activation bath is 5:1. On the other hand, when the layer of silicon rich material is deposited on the layer of diffusion barrier material, the ratio of the tin ion concentration to the palladium ion concentration in the activation bath is one of 3:1 or 5:2. Alternatively, when the layer of silicon rich material that is comprised of substantially only silicon atoms is deposited on the layer of diffusion barrier material, the ratio of the tin ion concentration to the palladium ion concentration in the activation bath is 2:1.
In an example embodiment of the present invention, the layer of seed material and the conductive fill material are comprised of copper, and the layer of diffusion barrier material is comprised of titanium silicon nitride (TiSiN). The present invention may be advantageously used when the interconnect opening is one of a metal line, a via hole, or a dual damascene opening.
In this manner, the activation layer of palladium is formed with higher nuclei density and uniformity to prevent agglomeration of the activation layer as the thickness of the activation layer is scaled down to tens of angstroms. Such a uniform activation layer in turn results in uniform deposition of the copper seed layer which prevents formation of voids within the copper interconnect for minimizing electromigration failure of the copper interconnect. In addition, the thinner activation layer advantageously results in minimized resistance of the copper interconnect.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.